//FileName   : reqs_gen
//Author     : -
//Description: reqs_gen
//ModifyDate : 2019-5-4
//Company    : -
//Copy right : -


module reqs_gen (
    input               clk,
    input               rst_n,
    input               dmem_cs,
    input               dmem_we,
    input     [19:0]    dmem_adr,
    output              test_cnt_eq_27,
    output              test_cnt_eq_3,
    output              test_cnt_eq_11
);

//internal wire define

//internal temp define
reg [4:0]     test_cnt;



//---------------------------------------------
//Function: AA
//---------------------------------------------

always @(posedge clk)
begin
    if(!rst_n)
        test_cnt <= 5'd0;
    else begin
    if( dmem_cs& dmem_we&( dmem_adr==20'h40) )
        test_cnt <= 5'd1;
    else if( |test_cnt )
        test_cnt <= test_cnt+5'd1;
    end
end

assign test_cnt_eq_27 = test_cnt>=5'd27;

assign test_cnt_eq_3 = test_cnt==5'd3;

assign test_cnt_eq_11 = test_cnt==5'd11;

endmodule
